Multi-character electronic display

ABSTRACT

Disclosed are multiple character electronic display devices utilizing plurality of character matrices, each of which includes plurality of thermally isolated semiconductor mesas which are heated by current passed through a resistance. The current in each mesa is controlled by a transistor formed therein, and such transistors may have a common collector voltage and a common emitter voltage supply lead which may be individually closed by a switch to enable a desired character. The bases of the transistors of corresponding mesas in all of the character matrices may be connected to common control lines to that all character matrices may be controlled by the same character generator. A particular diffusion pattern for the individual elements of the matrices is also disclosed which utilizes an extended collector transistor having a longitudinally extending, double diffused tunnel to provide cross connections from the control lines to the base contacts of the elements of an array.

[ Aug. 13, 1974 [57] ABSTRACT Disclosed are multiple characterelectronic display devices utilizing plurality of character matrices,each of which includes plurality of thermally isolated semiconductormesas which are heated by current passed through a resistance. Thecurrent in each mesa is controlled by a transistor formed therein, andsuch transistors may have a common collector voltage and a commonemitter voltage supply lead which may be individually closed by a switchto enable a desired character. The bases of the transistors ofcorresponding mesas in all of the character matrices may be con nectedto common control lines to that all character matrices may be controlledby the same character generator. A particular diffusion pattern for theindividual elements of the matrices is also disclosed which utilizes anextended collector transistor having a longitudinally extending, doublediffused tunnel to provide cross connections from the control lines tothe base contacts of the elements of an array.

6 Claims, 6 Drawing Figures DISPLAY [75] Inventors: Clifford H.Ensminger; Edward M.

Ruggiero, both of Dallas, Tex.

[73] Assignee: Texas Instruments Incorporated,

Dallas, Tex.

Jan. 19, 1971 [21] Appl. No.: 107,831

Related US. Application Data Division of Ser. No. 788,261, Dec. 31,1968, Pat. No. 3,698,012.

219/216, 219/543, 340/324 R Int. Cl. 1105b 1/00 219/216, 543; 346/76 R;40/28; 340/166 EL, 324 R References Cited UNITED STATES PATENTS 2/1970Alexander et a1. 219/216 United States Patent [19 Ensminger et a1.

[ MULTl-CHARACTER ELECTRONIC [22] Filed:

[58] Field of Search...........

Primary Examiner-C. L. Albritton Attorney, Agent, or Firm-James T.Comfort CHARACTER SELECT SWITCH Tia b iz- CHARACTER GENERATOR PAIENIEDAUDI 31914 CHARACTER SELECT SWITCH F722 Tun- CHARACTER GENERATORPATENIEB AUGI 3 m4 sum 20$ 3 1 MULTI-CHARACTER ELECTRONIC DISPLAY Thisapplication is a division of application Ser. No. 788,261, filed Dec.31, 1968, now U.S. Pat. No. 3,698,012.

This invention relates generally to electronic displays, and moreparticularly relates to an integrated semiconductor display having aplurality of character generation matrices.

A multicharacter electronic display has previously been disclosed inU.S. Pat. No. 3,496,333. The printhead there described utilizes apluralityof matrices of thermally isolated semiconductor mesas eachcontaining a resistor for thermal heating and a diode for switchingcurrent through the resistor. While this device has many advantages overthe prior art devices,

one problem is that the voltage drop of the common bus lines and drivelines results in temperature gradients between adjacent elements,producing print density variations. Mismatches in thermal expansioncoefficients prevent material reduction of these voltage drops.

Single character electronic displays have. been devised and aredescribed. in copending U.S. Pat. No. 3,501,615 which haveadvantages-resulting. from the use of a switching. transistor on eachmatrix element and a buffer transistor on an adjacent integratedcircuit. This device has the advantage of lower control currents andmore uniform heating as a result of the gain of the transistor devices.However, it has not heretofore been considered practical to incorporatethis type of matrix into a multicharacter device because of the largenumber of devices and leads required.

This invention is concerned with the use of the transistor type ofcharacter matrix in such a manner asto overcome the problems of variableprinting density encountered in previous diode controlled multiplecharacter devices. This is achieved by utilizing the collector-basejunction of the transistors in the individual mesas for isolation duringswitching so-that a single character generator and single set of buffersmay be used to control all character matrices, and the individualcharacters selectively enabled by controlling the power supply to theindividual mesas.

The invention is also concerned with a particular element geometry whichprovides another level of interconnections to permit the high elementdensities required for good resolution;

The novel features believed characteristic of this invention are setforth in the appended claims. The invention itself, however, as well asother objects and advantages thereof, may best be understood byreference to the following detailed description of an illustrativeembodiment, when read in conjunction with the accompanying drawings,wherein:

FIG. 1 is a simplified plan view of an electronic display in accordancewith the present invention;

FIG. 2 is a partial perspective view-of a portion of an electronicdisplay in accordance with the present invention;

FIG. 3 is a schematic circuit diagram of an electronic display system inaccordance with the present inventron;

FIG. 4 is a schematic. layout of the interior face of the semiconductorelements of the arrays;

FIG. 5 is an enlarged schematic plan view of one of the individualelements shown in FIG. 4; and

FIG. 6 is a schematic circuit diagram of a portion of the matrixrepresented in FIG. 4.

Referring now to the drawings, and in particular to FIGS. 1 and 2, threefour-character electronic displaydevices in accordance with the presentinvention are indicated generally by the reference numerals 10a, 10b,and 10c. Each of the electronic display devices l0al0c includes fourcharacter matrices l2'a-12d. Each matrix includes a 5 X 7 array ofelements E,E each of which is air isolated around its periphery andwhich is bonded to a ceramic slice 17 by a thermal insulating epoxylayer 14. The devices 10,,l0, can be fabricated using the variousprocesses heretofore described in the above-referenced U.S. Pat. Nos.3,496,333 and 3,501,615 applications and copending U.S. application Ser.No. 650,821, filed July 3, 1967, and entitled Thermal Displays Using AirIsolated Integrated Circuits and Methods of Making Same.

As will be presently described, a transistor with a series resistor inthe collector branch is formed by a diffusion in the face of eachelement E adjacent the epoxy layer 14. Thin film circuits deposited onthe interior face of the semiconductor element are used to interconnectthe diffused devices into an integrated circuit. For example, element Ein each of the characters includes a transistor T anda resistor R (SeeFIG. 3),

and element E in each character includes transistor T and resistor R Thecollectors of all of the transistors T T of a particular character areconnected through the respective resistors R,R to a common collectorvoltage supply line 18; All of the emitters of the transistors T -T ofeach of the characters l2a-l2d are connected to common emitter supplylines 20a-20d, respectively. Each of the character matrices 12 may thenbe selectively enabled by selectively applying power across theresistor-transistor circuits of the elements of the particular matrix byclosing the appropriate emitter circuit 20.

As illustrated in FIG. 3, the collector circuits 18 of all characters inthe system are common, and the emitter circuits of each matrix areindividually selected by a character select switch 22.

The base contacts of the transistors of the corresponding elements ofall characters in the device are also common. For example, the bases oftransistors T of character matrices 12a-12d of all devices 10a10c areconnected to a common control line C,, and transistors T are connectedto a common control line C Of course, it will be understood that thebases of transistors T -T (not illustrated) would be connected tocorresponding control lines C -C only a portion of which are illustratedin other figures presently to be described. The control lines C -Cextend from a character generator 24 which decodes electrical logicsignal and produces a voltage sufficient to turn on the transistor T onthose control lines necessary to produce the desired character. Asmentioned, the control lines C,C are common to all character matrices inthe system, which may typically be eighty characters for a line, so thatonly one character generator and one set of output buffer transistorsare required. Higher speeds can be achieved, however, by utilizingparallelconnected multiple character generators and corresponding outputbuffer transistors for parallel selection and pulsing of correspondingcharacter matrices l2a-l2d) of each plural character electronic displaydevice (10a-10c).

In the operation of the system, the character select switch 22 wouldtypically scan from the left-hand character matrix to the right-handcharacter matrix in sequence by selectively connecting the commonemitter lines 20a-20c of the character matrices to ground. Then duringthe period that each particular character matrix is thus enabled, thecollector voltage supply is applied to the common collector lead 18 andthe character generator produces the positive voltage levels on thecontrol lines C -C necessary to generate the character to be displayedor printed at the selected position. For example, a positive voltage onthe control line C,, would turn transistor T of the enabled charactermatrix on, thus causing element E to be heated by the power dissipatedin resistor R The transistor connected to control lines at groundpotential would remain turned off". For example, if control line C is atground potential, transistor T of the enabled character would remainoff. It is important to note that the collector-base junctions of alltransistors of all disabled character matrices block current from thecollector supply voltage line 18 from passing through the common controllines and turning on the transistors T of the enabled matrix that shouldbe off to generate the desired character.

An alternative mode of selectively enabling a particular charactermatrix may also be employed. Instead of a common collector lead 18 forall character matrices, only the collectors of each matrix may be commonand the common collectors of the disabled character matrices leftfloating. Then the collector-base junction of each transistor, thecontrol line of which is positive, can be forward biased in each matrixin which the collector is floating. However, the collector-base junctionof all other transistors of the matrices are reverse biased and blockcurrent from returning to the enabled matrix on a control line that isotherwise not positive, in the same manner as the free floatingbase-emitter junctions of the disabled matrices in the circuitillustrated in the drawings.

Similarly, the free-floating base-emitter junctions of the disabledmatrices prevent current from passing from a positive control linethrough a forward biased base-emitter junction to common emitter line 20and back through the emitter-base junction to a control line that shouldnot be positive.

Another aspect of the present invention is illustrated in FIG. 4 whichdepicts the general layout of the elements E of the matrices l2a-l2c ofa device The highly repetitive array has been simplified in FIG. 4 withthe element E shown in greater detail in FIG. 5 as an example of thediffusion and contact geometry. N-type semiconductor material, which maybe starting material, N-type diffused into P-type, or epitaxially grown,forms an expanded collector region 30. A P-type base diffusion 34 and aP-type tunnel diffusion 36 are performed simultaneously in the startingmaterial. An N+ emitter diffusion 38 and N+ tunnel diffusion 40 areperformed simultaneously. The surface of the element E is coated with alayer of insulating material, such as silicon dioxide, and a collectorcontact opening 42, a base contact opening 44, an emitter contactopening 46, and a shorting contact opening 48 are formed on all elementsof the device. It will be noted that opening 48 extends across thejunction between diffused regions 36 and 40 to short the baseemitter ofthe potential NPN transistor formed by diffusions 36 and 40 and thecollector region 30. In addition, a control line contact is cut in theoxide at one of flve positions I-V depending upon which column theparticular element is located in. For example, elements E E etc. in thefirst column of the matrix would have contact openings at position I,elements E E etc. in the second column of the matrix would have openingscut at position II, etc. Since element E is in the third column, acontact opening 50 is made at position III.

A shorting lead 52 (all leads are shown in darkened outline in FIG. 5)electrically connects the diffused tunnel 40 to the base region 34through contact openings 48 and 44.

The control lines C C are formed on the insulating layer and extendtransversely across the rows of elements and are automaticallyelectrically connected to the base of the appropriate transistor throughthe contact opening at the position I-V, the diffused tunnel 40 andshorting contact 52. For example, control line C is connected to thebase of the transistor of element E through contact opening 50, thediffused tunnel 40, contact opening 48, shorting lead 52, and basecontact opening 44.

As can be seen in FIG. 4, the alternate rows of elements are inverted sothat a common conductor strip 54 extends throughthe collector contactopenings 42 of elements E -E of each of the successive charactermatrices 1211-120. Similarly, common ground strips 56a-56c extendthrough the emitter contact openings 46 of elements B 45 of matricesl2a-l2c, respectively. The collectors of elements E -E are connected tocollector supply voltage strip 58, the bases of elements B -E ofmatrices l2a-l2c are common to strips 6011-600, respectively, thecollectors of elements E E are common to strip 62, the emitters ofelements E ,,E of matrices l2a-l2c are common to strips 64a-64c,respectively, and the collectors of elements E ,-E are connected tostrip,66. The emitter strips 56a-56c, 60a-60c and 64a-64c are connectedto the common character select lines 20a-20c, respectively. COmrOl lineSC1-C5, Cs-Cw, G -C Cw-Cgo,

C C C ,,C and C ,-C extend over elements l 51 rr- 10 ll 15 ur- 201 21-2s ar- 30 and E ,E, of all matrices 12a-l2d of all devices 10,, in thesystem, if desired.

The schematic circuit diagram for the elements shown in FIG. 4 areillustrated in FIG. 6 wherein corresponding parts are designated by thecorresponding reference characters.

Although the transistors described above with regard to a preferredembodiment of this invention are NPN type, PNP type could be employed inlieu thereof. Also in the above described preferred embodiment theresistance for heating each mesa of each matrix is the collectorsaturating resistance of the diffused transistor. Such resistance can bea separate component formed in or on each mesa of each matrix. It isalso contemplated that other size arrays, e.g., 7 X 9, I I X 15, may

ations can be made therein without departing from the spirit and scopeof the invention.

What is claimed is:

1. In a switching matrix, the combination of: a plurality of sets oftransistors, each set having a corresponding number, first circuit meanscommon to the collectors of the transistors of each set, including aresistive heating element connecting the collectors of the respectivetransistors to a common point, second circuit means common to theemitters of the transistors of each set, including a resistive heatingelement connecting the collectors of the respective transistors to acommon point, and a separate control line common to the bases of thecorresponding transistors of each set of transistors whereby each set oftransistors may be selectively enabled by connecting a supply voltagebetween the first and second circuit means for the set and theindividual transistors in the enabled set may be turned on by a voltageapplied to the respective control line, the resistive heating elementsof each set being arrayed in a character matrix of an electronicdisplay.

2. The combination of claim 1 wherein:

each resistive heating element and the transistor to which it isconnected are formed by a semiconductor mesa, and the semiconductormesas are isolated by a thermal discontinuity.

3. The combination of claim 2 wherein:

the semiconductor mesas are mounted on a supporting chip by a layer ofthermally insulating material in at least one row with the transistorsadjacent the insulating material,

each mesa includes an extended collector region extending normal to therow, a collector contact formed at one end of the collector region, abase region and an emitter region formed at the other end of thecollector region, with a base contact between the collector contact andan emitter contact,

an insulating layer over the mesas having collector,

base and emitter contact openings,

one level of electrical leads including a collector lead extending overthe collector contact openings of the mesas in the row, an emitter leadextending over the emitter contact openings of the mesas of the row, anda plurality of control leads disposed between the collector and emitterleads, and

another level of interconnections connecting selected control leads toselected base contacts.

4. The combination of claim 3 wherein:

said another level of interconnections comprises a tunnel in eachsemiconductor mesa.

5. The combination of claim 4 wherein:

the tunnel is comprised of an emitter diffusion in a base diffusion inthe collector region.

6. The combination of claim 3 wherein:

there are a plurality of rows of mesas arrayed to form a plurality ofcharacter matrices, and

the mesas in alternate rows are inverted such that the collector andemitter contacts of the transistors in each row are adjacent thecollector and emitter contacts, respectively, of the adjacent rows ofmesas.

1. In a switching matrix, the combination of: a plurality of sets oftransistors, each set having a corresponding number, first circuit meanscommon to the collectors of the transistors of each set, including aresistive heating element connecting the collectors of the respectivetransistors to a common point, second circuit means common to theemitters of the transistors of each set, including a resistive heatingelement connecting the collectors of the respective transistors to acommon point, and a separate control line common to the bases of thecorresponding transistors of each set of transistors whereby each set oftransistors may be selectively enabled by connecting a supply voltagebetween the first and second circuit means for the set and theindividual transistors in the enabled set may be turned on by a voltageapplied to the respective control line, the resistive heating elementsof each set being arrayed in a character matrix of an electronicdisplay.
 2. The combination of claim 1 wherein: each resistive heatingelement and the transistor to which it is connected are formed by asemiconductor mesa, and the semiconductor mesas are isolated by athermal discontinuity.
 3. The combination of claim 2 wherein: thesemiconductor mesas are mounted on a supporting chip by a layer ofthermally insulating material in at least one row with the transistorsadjacent the insulating material, each mesa includes an extendedcollector region extending normal to the row, a collector contact formedat one end of the collector region, a base region and an emitter regionformed at the other end of the collector region, with a base contactbetween the collector contact and an emitter contact, an insulatinglayer over the mesas having collector, base and emitter contactopenings, one level of electrical leads including a collector leadextending over the collector contact openings of the mesas in the row,an emitter lead extending over the emitter contact openings of the mesasof the row, and a plurality of control leads disposed between thecollector and emitter leads, and another level of interconnectionsconnecting selected control leads to selected base contacts.
 4. Thecombination of claim 3 wherein: said another level of interconnectionscomprises a tunnel in each semiconductor mesa.
 5. The combination ofclaim 4 wherein: the tunnel is comprised of an emitter diffusion in abase diffusion in the collector region.
 6. The combination of claim 3wherein: there are a plurality of rows of mesas arrayed to form aplurality of character matrices, and the mesas in alternate rows areinverted such that the collector and emitter contacts of the transistorsin each row are adjacent the collector and emitter contacts,respectively, of the adjacent rows of mesas.